A common requirement for advanced integrated circuits (“ICs”) in semiconductor processes is the use of through vias. In integrated circuit packages, the through vias allow vertical connections between devices and either integrated circuits mounted on a substrate, or to the substrate itself. For stacked package arrangements, the connections may extend through the substrate and allow stacked devices to be coupled through vertical paths. Through silicon vias (TSVs) may extend vertically through an integrated circuit or substrate and pass entirely through the device with or without electrical connections to the device. The use of these packaging technologies allows stacking of similar or different integrated circuit devices to add components without increased board area, for example. Unpackaged components may be arranged to be stacked within a package. Alternatively, packaged devices may be stacked using through vias to vertically couple the devices.
Forming deep holes, such as through vias, or blind vias (vias that extend into, but not through, a layer) using photolithography and etching operations is difficult. The vias must be formed correctly in increasingly thick layers of material and then plugged, plated or otherwise filled with conductive materials. The use of conventional photoresist, pattern, and etch steps to form the vias requires complex chemical processes and may also pose additional process control challenges, defects due to non-uniform processing may occur. Many steps are needed to form the patterns. Chemicals are used in photolithographic processes which add expense and create environmental problems.
The through vias may be formed in a package mounted on a substrate. In an application, an integrated circuit may be mounted on a substrate. The integrated circuit may be a processor, DSP, memory, FLASH, EEPROM or other device and may be quite sophisticated, such as a “system on a chip” or “SoC” device, or may be a simple transceiver or memory device. The substrate may include some circuitry such as redistribution metal layers, wire traces, solder ball or bumps connections, pin grid arrays, or other board level connectors, and may include one or more other integrated circuits, or passive or active devices such as decoupling capacitors for example. Substrates may be made of BT resin or “green board”, epoxy resin, ceramic, plastic, silicon, glass or other materials. In an increasingly common arrangement for stacked packaging, the substrate may in fact itself be an integrated circuit, or a silicon substrate having passive or active circuitry formed within it. Alternatively, the substrate may be a blank wafer or a silicon or other semiconductor substrate.
As sophisticated electronic devices continue to become smaller and often are provided in portable, battery powered forms, such as tablet computers, PDAs, and smart phones, circuit board area and board size become more critical. The increased use of stacking and vertical packaging arrangements is therefore continuing and accelerating in industry. This increase in vertical integration of devices makes through via connections more important and more prevalent, and thus there is an increasing need to form these connections in a high yield, low cost, robust and efficient manner.
A continuing need thus exists for through via connection equipment and methods that overcome the disadvantages of the prior art approaches.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.